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Features
* MPEG I/II-Layer 3 Hardwired Decoder
- Stand-alone MP3 Decoder - 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency - Separated Digital Volume Control on Left and Right Channels (Software Control using 31 Steps) - Bass, Medium, and Treble Control (31 Steps) - Bass Boost Sound Effect - Ancillary Data Extraction - CRC Error and MPEG Frame Synchronization Indicators Programmable Audio Output for Interfacing with Common Audio DAC - PCM Format Compatible - I2S Format Compatible 8-bit MCU C51 Core Based (F MAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory - AT89C51SND1C: Flash (100K Erase/Write Cycles) - AT83SND1C: ROM 4K Bytes of Boot Flash Memory (AT89C51SND1C) - ISP: Download from USB or UART External Code Memory - AT80C51SND1C: ROMless USB Rev 1.1 Controller - Full Speed Data Transmission Built-in PLL - MP3 Audio Clocks - USB Clock MultiMedia Card (R) Interface Compatibility Atmel DataFlash (R) SPI Interface Compatibility IDE/ATAPI Interface 2 Channels 10-bit ADC, 8 kHz (8-true bit) - Battery Voltage Monitoring - Voice Recording Controlled by Software Up to 44 Bits of General-purpose I/Os - 4-bit Interrupt Keyboard Port for a 4 x n Matrix - SmartMedia (R) Software Interface 2 Standard 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management - Power-on Reset - Software Programmable MCU Clock - Idle Mode, Power-down Mode Operating Conditions: - 3V, 10%, 25 mA Typical Operating at 25C - Temperature Range: -40C to +85C Packages - TQFP80, BGA81, PLCC84 (Development Board) - Dice
* * * * * * * * * * * * * * * * * * *
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
AT83SND1C AT89C51SND1C AT80C51SND1C
* *
Rev. 4109FS-8051-01/04
Description
The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory. The AT83SND1C includes 64K Bytes of ROM memory. The AT80C51SND1C does not include any code memory. The AT8xC51SND1C include 2304 Bytes of RAM memory. The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
Typical Applications
* * * *
MP3-Player PDA, Camera, Mobile Phone MP3 Car Audio/Multimedia MP3 Home Audio/Multimedia MP3
Block Diagram
Figure 1. AT8xC51SND1C Block Diagram
INT0 INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD T0 T1 SS MISO MOSI SCK SCL SDA
3
3 Interrupt Handler Unit Flash ROM 64 KBytes Flash Boot 4 KBytes
3
3
3
3
4
4
4
4
1
1
RAM 2304 Bytes
10-bit A to D Converter or 10-bit ADC
UART and BRG
Timers 0/1 Watchdog
SPI/DataFlash Controller
TWI Controller
C51 (X2 Core)
8-Bit Internal Bus
Clock and PLL Unit
MP3 Decoder Unit
I2S/PCM Audio Interface
USB Controller
MMC Interface
Keyboard Interface
I/O Ports IDE Interface
1
FILT X1 X2 RST ISP ALE DOUT DCLK DSEL SCLK D+ DMCLK MDAT MCMD KIN3:0 P0-P5
1 Alternate function of Port 1 3 Alternate function of Port 3 4 Alternate function of Port 4
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AT8xC51SND1C
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AT8xC51SND1C
Pin Description
Pinouts
Figure 2. AT8xC51SND1C 80-pin QFP Package
P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
ALE ISP1/PSEN2/NC P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PVDD FILT PVSS VSS X2 X1 TST UVDD UVSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
AT89C51SND1C-RO (FLASH) AT83SND1C-RO (ROM) AT80C51SND1C-RO (ROMLESS)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD
Notes:
1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C product. 2. PSEN pin is only available in AT80C51SND1C product.
D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Figure 3. AT8xC51SND1C 81-pin BGA Package
9
P4.6
8
P2.0/ A8
7
P4.0/ MISO P4.1/ MOSI P2.1/ A9
6
P4.2/ SCK P4.3/ SS
5
VDD
4
P0.2/ AD2 P0.4/ AD4
3
P0.3/ AD3 P0.0/ AD0 P1.0/ KIN0 P1.7/ SDA
2
P5.0 ISP1/ PSEN2 NC P1.3/ KIN3
1
ALE
A B C D E F G H J
P4.4
P4.7
P0.1/ AD1
P1.1
P2.5/ A13 P2.4/ A12
P2.2/ A10 P2.6/ A14 P2.3/ A11
P0.6
VSS
P5.1
P1.2/ KIN2
P4.5
P0.7/ AD7 P2.7/ A15
P0.5/ AD5
P1.6/ SCL
P1.5
P1.4
VDD
VSS
FILT
PVDD
X1
VDD
RST
MCMD
MCLK
MDAT
AVDD
P3.4/ T0 P3.5/ T1 P3.3/ INT1 P3.2/ INT0
UVSS
PVSS
X2
DSEL
SCLK
DOUT
P5.3
P3.7/ RD
VDD
TST
VSS
DCLK
VSS
AIN1
AVSS
AIN0
P3.1/ TXD P3.0/ RXD
D-
UVDD
VDD
P5.2
AREFP
AREFN
P3.6/ WR
VSS
D+
Notes:
1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C and AT80C51SND1C product. 2. PSEN pin is only available in AT80C51SND1C product.
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AT8xC51SND1C
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AT8xC51SND1C
Figure 4. AT8xC51SND1C 84-pin PLCC Package
NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PAVDD FILT PAVSS VSS X2 NC X1 TST UVDD UVSS 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
AT89C51SND1C-SR (FLASH)
NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD
D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
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Signals
All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description
Signal Name Type Description Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function
P0.7:0
I/O
AD7:0
P1.7:0
I/O
KIN3:0 SCL SDA A15:8 RXD TXD
P2.7:0
I/O
P3.7:0
I/O
Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups.
INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS -
P4.7:0
I/O
Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups.
P5.3:0
I/O
Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal Name Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. Alternate Function
X1
I
-
X2
O
-
FILT
I
-
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Table 3. Timer 0 and Timer 1 Signal Description
Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low level on INT1#. Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.3 P3.2 Alternate Function
T0
I
P3.4
T1
I
P3.5
Table 4. Audio Interface Signal Description
Signal Name DCLK DOUT DSEL Type O O O Description DAC Data Bit Clock DAC Audio Data DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function -
SCLK
O
-
Table 5. USB Controller Signal Description
Signal Name Type Description USB Positive Data Upstream Port This pin requires an external 1.5 K pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function
D+
I/O
-
D-
I/O
-
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4109FS-8051-01/04
Table 6. MutiMediaCard Interface Signal Description
Signal Name MCLK Type O Description MMC Clock output Data or command clock transfer. MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS. Alternate Function -
MCMD
I/O
-
MDAT
I/O
-
Table 7. UART Signal Description
Signal Name Type Description Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Alternate Function
RXD
I/O
P3.0
TXD
O
P3.1
Table 8. SPI Controller Signal Description
Signal Name Type Description SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. SPI Slave Select Line When in controlled slave mode, SS enables the slave mode. Alternate Function
MISO
I/O
P4.0
MOSI
I/O
P4.1
SCK
I/O
P4.2
SS
I
P4.3
Table 9. TWI Controller Signal Description
Signal Name Type Description TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. TWI Serial Data SDA is the bidirectional Two Wire data line. Alternate Function
SCL
I/O
P1.6
SDA
I/O
P1.7
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AT8xC51SND1C
Table 10. A/D Converter Signal Description
Signal Name AIN1:0 AREFP AREFN Type I I I Description A/D Converter Analog Inputs Analog Positive Voltage Reference Input Analog Negative Voltage Reference Input This pin is internally connected to AVSS. Alternate Function -
Table 11. Keypad Interface Signal Description
Signal Name Type Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. Alternate Function
KIN3:0
I
P1.3:0
Table 12. External Access Signal Description
Signal Name Type Description Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE interface. Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. Program Store Enable Output (AT80C51SND1C Only) This signal is active low during external code fetch or external code read (MOVC instruction). ISP Enable Input (AT89C51SND1C Only) This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. Read Signal Read signal asserted during external data memory read operation. Write Signal Write signal asserted during external data memory write operation. Alternate Function
A15:8
I/O
P2.7:0
AD7:0
I/O
P0.7:0
ALE
O
-
PSEN
I/O
-
ISP
I/O
-
RD
O
P3.7
WR
O
P3.6
9
4109FS-8051-01/04
Table 13. System Signal Description
Signal Name Type Description Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. Test Input Test mode entry signal. This pin must be set to VDD. Alternate Function
RST
I
-
TST
I
-
Table 14. Power Signal Description
Signal Name VDD Type PWR Description Digital Supply Voltage Connect these pins to +3V supply voltage. Circuit Ground Connect these pins to ground. Analog Supply Voltage Connect this pin to +3V supply voltage. Analog Ground Connect this pin to ground. PLL Supply voltage Connect this pin to +3V supply voltage. PLL Circuit Ground Connect this pin to ground. USB Supply Voltage Connect this pin to +3V supply voltage. USB Ground Connect this pin to ground. Alternate Function -
VSS
GND
-
AVDD
PWR
-
AVSS
GND
-
PVDD
PWR
-
PVSS
GND
-
UVDD
PWR
-
UVSS
GND
-
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Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1)
VDD
Type
Pins
RTST
Input
TST
VDD
Watchdog Output
P Input/Output
RRST
RST
VSS
2 osc periods Latch Output
VDD
VDD
VDD
P1
P2
P3 Input/Output
N
VSS VDD
P1(2) P2(3) P3 P4 P53:0
P Input/Output N
VSS VDD
P0 MCMD MDAT ISP PSEN
P Output N
VSS
ALE SCLK DCLK DOUT DSEL MCLK
D+ D-
Input/Output
D+ D-
Notes:
1. For information on resistors value, input/output levels, and drive capability, refer to the Section "DC Characteristics", page 29. 2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing pseudo open-drain structure. 3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
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AT8xC51SND1C
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AT8xC51SND1C
Figure 5.
13
4109FS-8051-01/04
Application Information
Figure 6. AT8xC51SND1C Typical Application with On-Board Atmel DataFlash and 2wire LCD
LCD
Battery
Ref.
P1.6/SCL P1.7/SDA
VREFN
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 X1 X2
VREFP
AVDD
AIN1
AIN0
VDD
RST
MCLK MDAT MCMD
MMC1 MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P4.2/SCK
P4.0/SI
DOUT DCLK DSEL SCLK
FILT PVSS P4n
P4.1/SO
DataFlash Memories
Audio DAC
14
AT8xC51SND1C
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AVSS
P1.4
P1.5
VSS
AT8xC51SND1C
Figure 7. AT8xC51SND1C Typical Application with On-Board Atmel DataFlash and // LCD
LCD
Battery
P1.6/SCL P1.7/SDA
Ref.
P1.3 P0.4 P0.5 P0.6 P0.7
VREFN
VREFP
AVDD
AIN1
AIN0
VDD
RST
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 X1 X2
MCLK MDAT MCMD
MMC1 MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P4.2/SCK
P4.0/SI
DOUT DCLK DSEL SCLK
FILT P4.n PVSS
P4.1/SO
DataFlash Memories
Audio DAC
AVSS
P1.4
P1.5
VSS
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Figure 8. AT8xC51SND1C Typical Application with On-Board SSFDC Flash
LCD
Battery
Ref.
P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7
VREFP
VREFN
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 X1 X2
AVDD
AIN1
AIN0
VDD
RST
MCLK MDAT MCMD
MMC1 MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P3.6/WR#
DOUT DCLK DSEL SCLK
FILT P2 PVSS P0
P3.7/RD#
Audio DAC SSFDC Memories or SmartMedia Cards
SmartMedia
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AT8xC51SND1C
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AVSS
P3.4
P3.5
VSS
AT8xC51SND1C
Figure 9. AT8xC51SND1C Typical Application with IDE CD-ROM Drive
LCD
Battery
P1.6/SCL P1.7/SDA
Ref.
P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7
VREFP
VREFN
AVDD
AIN1
AIN0
VDD
RST
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 X1 X2 P3.6/WR# FILT P2 PVSS P0
MCLK MDAT MCMD
MMC1 MMC2
AT8xC51SND1C
UVDD D+ DUVSS
USB PORT
P3.7/RD#
DOUT DCLK DSEL SCLK
Audio DAC IDE CD-ROM
AVSS
P3.4
P3.5
VSS
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Address Spaces
The AT8xC51SND1C derivatives implement four different address spaces: * * * * Program/Code Memory Boot Memory Data Memory Special Function Registers (SFRs)
Code Memory
The AT89C51SND1C and AT83SND1C implement 64 Kbytes of on-chip program/code memory. The AT83SND1C product provides the internal program/code memory in ROM technology while the AT89C51SND1C product provides it in FLASH technology. The FLASH memory increases ROM functionality by enabling in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing FLASH cells is generated on-chip using the standard VDD voltage. Thus, the AT89C51SND1C can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tool.
Boot Memory
The AT89C51SND1C implements 4 Kbytes of on-chip boot memory provided in FLASH technology. This boot memory is delivered programmed with a standard boot loader software allowing in system programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop its own boot loader.
Data Memory
The AT89C51SND1C derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas: * * 256 bytes of on-chip RAM memory (standard C51 memory). 2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions).
Special Function Registers
The Special Function Registers (SFRs) of the AT89C51SND1C derivatives fall into the categories detailed in Table 1 to Table 17. The relative addresses of these SFRs are provided together with their reset values in Table 18. In this table, the bit-addressable registers are identified by Note 1.
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Table 1. C51 Core SFRs
Mnemonic ACC B PSW SP DPL Add E0h F0h D0h 81h 82h Name Accumulator B Register Program Status Word Stack Pointer Data Pointer Low byte Data Pointer High byte CY AC F0 RS1 RS0 OV F1 P 7 6 5 4 3 2 1 0
DPH
83h
Table 2. System Management SFRs
Mnemonic PCON AUXR AUXR1 NVERS Add 87h 8Eh A2h Name Power Control Auxiliary Register 0 Auxiliary Register 1 7 SMOD1 NV7 6 SMOD0 EXT16 NV6 5 M0 ENBOOT NV5 4 DPHDIS NV4 3 GF1 XRS1 GF3 NV3 2 GF0 XRS0 0 NV2 1 PD EXTRAM NV1 0 IDL AO DPS NV0
FBh Version Number
Table 3. PLL & System Clock SFRs
Mnemonic CKCON PLLCON PLLNDIV PLLRDIV Add 8Fh E9h Name Clock Control PLL Control 7 R1 R9 6 R0 N6 R8 5 N5 R7 4 N4 R6 3 PLLRES N3 R5 2 N2 R4 1 PLLEN N1 R3 0 X2 PLOCK N0 R2
EEh PLL N Divider EFh PLL R Divider
Table 4. Interrupt SFRs
Mnemonic IEN0 Add A8h Name Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control High 0 Interrupt Priority Control Low 0 Interrupt Priority Control High 1 Interrupt Priority Control Low 1 7 EA 6 EAUD 5 EMP3 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
IEN1
B1h
-
EUSB
-
EKB
EADC
ESPI
EI2C
EMMC
IPH0
B7h
-
IPHAUD
IPHMP3
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
IPL0
B8h
-
IPLAUD
IPLMP3
IPLS
IPLT1
IPLX1
IPLT0
IPLX0
IPH1
B3h
-
IPHUSB
-
IPHKB
IPHADC
IPHSPI
IPHI2C
IPHMMC
IPL1
B2h
-
IPLUSB
-
IPLKB
IPLADC
IPLSPI
IPLI2C
IPLMMC
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Table 5. Port SFRs
Mnemonic P0 P1 P2 P3 P4 P5 Add 80h 90h A0h B0h Name 8-bit Port 0 8-bit Port 1 8-bit Port 2 8-bit Port 3 7 6 5 4 3 2 1 0
C0h 8-bit Port 4
-
D8h 4-bit Port 5
Table 6. Flash Memory SFR
Mnemonic FCON Add Name 7 FPL3 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD1 1 FMOD0 0 FBUSY
D1h Flash Control
Table 7. Timer SFRs
Mnemonic TCON Add 88h Name Timer/Counter 0 and 1 Control Timer/Counter 0 and 1 Modes Timer/Counter 0 Low Byte Timer/Counter 0 High Byte Timer/Counter 1 Low Byte Timer/Counter 1 High Byte WatchDog Timer Reset WatchDog Timer Program WTO2 WTO1 WTO0 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
TMOD
89h
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
TL0
8Ah
TH0
8Ch
TL1
8Bh
TH1
8Dh
WDTRST
A6h
WDTPRG
A7h
Table 8. MP3 Decoder SFRs
Mnemonic MP3CON MP3STA MP3STA1 Add Name 7 MPEN MPANC 6 MPBBST MPREQ 5 CRCEN ERRLAY 4 MSKANC ERRSYN MPFREQ 3 MSKREQ ERRCRC MPBREQ 2 MSKLAY MPFS1 1 MSKSYN MPFS0 0 MSKCRC MPVER -
AAh MP3 Control C8h MP3 Status AFh MP3 Status 1
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Mnemonic MP3DAT MP3ANC MP3VOL Add Name 7 MPD7 AND7 6 MPD6 AND6 5 MPD5 AND5 4 MPD4 AND4 VOL4 3 MPD3 AND3 VOL3 2 MPD2 AND2 VOL2 1 MPD1 AND1 VOL1 0 MPD0 AND0 VOL0
ACh MP3 Data ADh MP3 Ancillary Data 9Eh MP3 Audio Volume Control Left MP3 Audio Volume Control Right MP3 Audio Bass Control MP3 Audio Medium Control MP3 Audio Treble Control
MP3VOR
9Fh
-
-
-
VOR4
VOR3
VOR2
VOR1
VOR0
MP3BAS
B4h
-
-
-
BAS4
BAS3
BAS2
BAS1
BAS0
MP3MED
B5h
-
-
-
MED4
MED3
MED2
MED1
MED0
MP3TRE MP3CLK
B6h
-
-
-
TRE4 MPCD4
TRE3 MPCD3
TRE2 MPCD2
TRE1 MPCD1
TRE0 MPCD0
EBh MP3 Clock Divider
Table 9. Audio Interface SFRs
Mnemonic AUDCON0 AUDCON1 AUDSTA AUDDAT AUDCLK Add 9Ah 9Bh Name Audio Control 0 Audio Control 1 7 JUST4 SRC SREQ AUD7 6 JUST3 DRQEN UDRN AUD6 5 JUST2 MSREQ AUBUSY AUD5 4 JUST1 MUDRN AUD4 AUCD4 3 JUST0 AUD3 AUCD3 2 POL DUP1 AUD2 AUCD2 1 DSIZ DUP0 AUD1 AUCD1 0 HLR AUDEN AUD0 AUCD0
9Ch Audio Status 9Dh Audio Data ECh Audio Clock Divider
Table 10. USB Controller SFRs
Mnemonic USBCON USBADDR USBINT USBIEN Add Name 7 USBE FEN 6 SUSPCLK UADD6 5 SDRMWUP UADD5 WUPCPU EWUPCPU 4 UADD4 EORINT EEORINT 3 UPRSM UADD3 SOFINT ESOFINT 2 RMWUPE UADD2 1 CONFG UADD1 0 FADDEN UADD0 SPINT ESPINT
BCh USB Global Control C6h USB Address BDh USB Global Interrupt BEh USB Global Interrupt Enable USB Endpoint Number USB Endpoint X Control USB Endpoint X Status
UEPNUM
C7h
-
-
-
-
-
-
EPNUM1
EPNUM0
UEPCONX
D4h
EPEN
-
-
-
DTGL
EPDIR
EPTYPE1
EPTYPE0
UEPSTAX UEPRST UEPINT
CEh
DIR -
-
STALLRQ -
TXRDY -
STLCRC EP3RST EP3INT
RXSETUP EP2RST EP2INT
RXOUT EP1RST EP1INT
TXCMP EP0RST EP0INT
D5h USB Endpoint Reset F8h USB Endpoint Interrupt USB Endpoint Interrupt Enable
UEPIEN
C2h
-
-
-
-
EP3INTE
EP2INTE
EP1INTE
EP0INTE
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4109FS-8051-01/04
Mnemonic UEPDATX
Add CFh
Name USB Endpoint X Fifo Data USB Endpoint X Byte Counter USB Frame Number Low USB Frame Number High
7 FDAT7
6 FDAT6
5 FDAT5
4 FDAT4
3 FDAT3
2 FDAT2
1 FDAT1
0 FDAT0
UBYCTX
E2h
-
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
UFNUML
BAh
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
UFNUMH USBCLK
BBh
-
-
CRCOK -
CRCERR -
-
FNUM10 -
FNUM9 USBCD1
FNUM8 USBCD0
EAh USB Clock Divider
Table 11. MMC Controller SFRs
Mnemonic MMCON0 MMCON1 MMCON2 Add E4h E5h E6h Name MMC Control 0 MMC Control 1 MMC Control 2 MMC Control and Status MMC Interrupt 7 DRPTR BLEN3 MMCE N MCBI MCBM MC7 MD7 MMCD 7 6 DTPTR BLEN2 DCR 5 CRPTR BLEN1 CCR 4 CTPTR BLEN0 3 MBLOCK DATDIR 2 DFMT DATEN DATD1 1 RFMT RESPEN DATD0 0 CRCDIS CMDEN FLOWC
MMSTA MMINT MMMSK MMCMD MMDAT MMCLK
DEh E7h
EORI EORM MC6 MD6 MMCD6
CBUSY EOCI EOCM MC5 MD5 MMCD5
CRC16S EOFI EOFM MC4 MD4 MMCD4
DATFS F2FI F2FM MC3 MD3 MMCD3
CRC7S F1FI F1FM MC2 MD2 MMCD2
RESPFS F2EI F2EM MC1 MD1 MMCD1
CFLCK F1EI F1EM MC0 MD0 MMCD0
DFh MMC Interrupt Mask DDh MMC Command DCh MMC Data EDh MMC Clock Divider
Table 12. IDE Interface SFR
Mnemonic DAT16H Add F9h Name High Order Data Byte 7 D15 6 D14 5 D13 4 D12 3 D11 2 D10 1 D9 0 D8
Table 13. Serial I/O Port SFRs
Mnemonic SCON SBUF SADEN SADDR BDRCON BRL Add 98h 99h B9h A9h 92h 91h Name Serial Control Serial Data Buffer Slave Address Mask Slave Address Baud Rate Control Baud Rate Reload BRR TBCK RBCK SPD SRC 7 FE/SM 0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
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Table 14. SPI Controller SFRs
Mnemonic SPCON SPSTA SPDAT Add Name 7 SPR2 SPIF SPD7 6 SPEN WCOL SPD6 5 SSDIS SPD5 4 MSTR MODF SPD4 3 CPOL SPD3 2 CPHA SPD2 1 SPR1 SPD1 0 SPR0 SPD0
C3h SPI Control C4h SPI Status C5h SPI Data
Table 15. 2-wire Controller SFRs
Mnemonic SSCON Add 93h Name Synchronous Serial control Synchronous Serial Status Synchronous Serial Data Synchronous Serial Address 7 SSCR2 6 SSPE 5 SSSTA 4 SSSTO 3 SSI 2 SSAA 1 SSCR1 0 SSCR0
SSSTA
94h
SSC4
SSC3
SSC2
SSC1
SSC0
0
0
0
SSDAT
95h
SSD7
SSD6
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
SSADR
96h
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSGC
Table 16. Keyboard Interface SFRs
Mnemonic KBCON KBSTA Add A3h A4h Name Keyboard Control Keyboard Status 7 KINL3 KPDE 6 KINL2 5 KINL1 4 KINL0 3 KINM3 KINF3 2 KINM2 KINF2 1 KINM1 KINF1 0 KINM0 KINF0
Table 17. A/D Controller SFRs
Mnemonic ADCON ADCLK ADDL ADDH Add F3h F2h F4h F5h Name ADC Control ADC Clock Divider ADC Data Low Byte ADC Data High Byte 7 ADAT9 6 ADIDL ADAT8 5 ADEN ADAT7 4 ADEOC ADCD4 ADAT6 3 ADSST ADCD3 ADAT5 2 ADCD2 ADAT4 1 ADCD1 ADAT1 ADAT3 0 ADCS ADCD0 ADAT0 ADAT2
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Table 18. SFR Addresses and Reset Values
0/8 F8h UEPINT 0000 0000 B1 0000 0000 PLLCON 0000 1000 ACC1 0000 0000 P51 XXXX 1111 PSW1 0000 0000 MP3STA1 0000 0001 P41 1111 1111 IPL01 X000 0000 P31 1111 1111 IEN01 0000 0000 P21 1111 1111 SCON 0000 0000 P11 1111 1111 TCON1 0000 0000 P01 1111 1111 0/8 SBUF XXXX XXXX BRL 0000 0000 TMOD 0000 0000 SP 0000 0111 1/9 SADEN 0000 0000 IEN1 0000 0000 SADDR 0000 0000 UEPIEN 0000 0000 UFNUML 0000 0000 IPL1 0000 0000 MP3CON 0011 1111 AUXR1 XXXX 00X0 AUDCON0 0000 1000 BDRCON XXX0 0000 TL0 0000 0000 DPL 0000 0000 2/A Reserved KBCON 0000 1111 AUDCON1 1011 0010 SSCON 0000 0000 TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E SPCON 0001 0100 UFNUMH 0000 0000 IPH1 0000 0000 SPSTA 0000 0000 USBCON 0000 0000 MP3BAS 0000 0000 MP3DAT 0000 0000 KBSTA 0000 0000 AUDSTA 1100 0000 SSSTA 1111 1000 TH0 0000 0000 AUDDAT 1111 1111 SSDAT 1111 1111 TH1 0000 0000 SPDAT XXXX XXXX USBINT 0000 0000 MP3MED 0000 0000 MP3ANC 0000 0000 WDTRST 0000 1000 MP3VOL 0000 0000 SSADR 1111 1110 AUXR X000 1101 CKCON 0000 000X5 PCON XXXX 0000 7/F FCON3 1111 00004 1/9 DAT16H XXXX XXXX ADCLK 0000 0000 USBCLK 0000 0000 UBYCTLX 0000 0000 2/A 3/B NVERS2 1000 0010 ADCON 0000 0000 MP3CLK 0000 0000 ADDL 0000 0000 AUDCLK 0000 0000 MMCON0 0000 0000 MMDAT 1111 1111 UEPCONX 0000 0000 ADDH 0000 0000 MMCLK 0000 0000 MMCON1 0000 0000 MMCMD 1111 1111 UEPRST 0000 0000 UEPSTAX 0000 0000 USBADDR 1000 0000 USBIEN 0001 0000 MP3TRE 0000 0000 IPH0 X000 0000 MP3STA1 0100 0001 WDTPRG 0000 1000 MP3VOR 0000 0000 UEPDATX 0000 0000 UEPNUM 0000 0000 PLLNDIV 0000 0000 MMCON2 0000 0000 MMSTA 0000 0000 PLLRDIV 0000 0000 MMINT 0000 0011 MMMSK 1111 1111 4/C 5/D 6/E 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h
D7h
C8h
CFh
C0h
C7h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
Notes:
1. SFR registers with least significant nibble address equal to 0 or 8 are bitaddressable. 2. NVERS reset value depends on the silicon version. 3. FCON register is only available in AT89C51SND1C product. 4. FCON reset value is 00h in case of reset with hardware condition. 5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
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Peripherals
The AT8xC51SND1C peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC51SND1C design guide.
Clock Generator System
The AT8xC51SND1C internal clocks are extracted from an on-chip PLL fed by an onchip oscillator. Four clocks are generated respectively for the C51 core, the MP3 decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The MP3 decoder clock is generated by dividing the PLL output clock. The audio interface sample rates are also obtained by dividing the PLL output clock.
Ports
The AT8xC51SND1C implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition to performing general-purpose I/O, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/O and alternate functions.
Timers/Counters
The AT8xC51SND1C implements the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request.
Watchdog Timer
The AT8xC51SND1C implements a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions.
MP3 Decoder
The AT8xC51SND1C implements a MPEG I/II audio layer 3 decoder (known as MP3 decoder). In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32 MBytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data. In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 KHz are supported for low bit rates applications. The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
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Additional features are supported by the AT8xC51SND1C MP3 decoder such as volume, bass, medium, and treble controls, bass boost effect and ancillary data extraction.
Audio Output Interface
The AT8xC51SND1C implements an audio output interface allowing the decoded audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I2S formats and thanks to the on-chip PLL (see Section ) allows connection of almost all of the commercial audio DAC families available on the market.
Universal Serial Bus Interface
The AT8xC51SND1C implements a full speed Universal Serial Bus Interface. It can be used for the following purposes: * * Download of MP3 encoded audio files by supporting the USB mass storage class. In System Programming by supporting the USB firmware upgrade class.
MultiMediaCard Interface
The AT8xC51SND1C implements a MultiMediaCard (MMC) interface compliant to the V2.2 specification in MultiMediaCard Mode. The MMC allows storage of MP3 encoded audio files in removable flash memory cards that can be easily plugged or removed from the application. It can also be used for In System Programming.
IDE/ATAPI interface
The AT8xC51SND1C provides an IDE/ATAPI interface allowing connexion of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive... It consists in a 16-bit bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In System Programming using CD-ROM.
Serial I/O Interface
The AT8xC51SND1C implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: * * In System Programming. Remote control of the AT8xC51SND1C by a host.
Serial Peripheral Interface
The AT8xC51SND1C implements a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes: * * * Interfacing DataFlash memory for MP3 encoded audio files storage. Remote control of the AT8xC51SND1C by a host. In System Programming.
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AT8xC51SND1C
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AT8xC51SND1C
2-wire Controller
The AT8xC51SND1C implements a 2-wire controller supporting the four standard master and slave modes with multimaster capability. It is provided for the following purposes: * * * Connection of slave devices like LCD controller, audio DAC... Remote control of the AT8xC51SND1C by a host. In System Programming.
A/D Controller
The AT8xC51SND1C implements a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). It is provided for the following purposes: * * * Battery monitoring. Voice recording. Corded remote control.
Keyboard Interface
The AT8xC51SND1C implements a keyboard interface allowing connection of 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes.
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Electrical Characteristics
Absolute Maximum Rating
Storage Temperature ......................................... -65 to +150C Voltage on any other Pin to V SS
.................................... -0.3
*NOTICE:
to +4.0 V
IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Operating Conditions Ambient Temperature Under Bias........................ -40 to +85C VDD ......................................................................................................... 2.7 to 3.3V
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
DC Characteristics
Digital Logic Table 16. Digital DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol VIL VIH1(2) VIH2 VOL1 Parameter Input Low Voltage Input High Voltage (except RST, X1) Input High Voltage (RST, X1) Output Low Voltage (except P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output Low Voltage (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output High Voltage (P1, P2, P3, P4 and P5) Output High Voltage (P0, P2 address mode, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) Logical 0 Input Current (P1, P2, P3, P4 and P5) Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Logical 1 to 0 Transition Current (P1, P2, P3, P4 and P5) Pull-Down Resistor Pin Capacitance VDD Data Retention Limit 50 90 10 1.8 VDD - 0.7 Min -0.5 0.2*VDD + 1.1 0.7*VDD Typ(1) Max 0.2*VDD - 0.1 VDD VDD + 0.5 0.45 Units V V V Test Conditions
V
IOL = 1.6 mA
VOL2
0.45
V
IOL = 3.2 mA
VOH1
V
IOH= -30 A
VOH2
VDD - 0.7
V
IOH= -3.2 mA
IIL
-50
A
VIN = 0.45 V
ILI
10
A
0.45< VIN< VDD
ITL RRST CIO VRET
-650 200
A k pF V
VIN = 2.0 V
TA= 25C
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Table 16. Digital DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol Parameter Min Typ(1) Max X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 X1 / X2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 X1 / X2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 X1 / X2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 20 500 Units Test Conditions VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VRET < VDD < 3.3 V VRET < VDD < 3.3 V VRET < VDD < 3.3 V VDD < 3.3 V
AT89C51SND1C Operating Current
(3)
IDD
AT83SND1C Operating Current
AT80C51SND1C Idle Mode Current
AT89C51SND1C Idle Mode Current
(3)
IDL
AT83SND1C Idle Mode Current
AT80C51SND1C Idle Mode Current
AT89C51SND1C Power-Down Mode Current IPD AT83SND1C Power-Down Mode Current AT80C51SND1C Power-Down Mode Current IFP AT89C51SND1C Flash Programming Current
A A A
20
500
20
500
15
mA
Notes:
1. Typical values are obtained using VDD= 3 V and TA= 25C. They are not tested and there is no guarantee on these values. 2. Flash retention is guaranteed with the same formula for VDD min down to 0V. 3. See Table 17 for typical consumption in player mode.
Table 17. Typical Reference Design AT89C51SND1C Power Consumption
Player Mode Stop IDD 10 mA Test Conditions AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V No song playing AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V MP3 Song with Fs= 44.1 KHz, at any bit rates (Variable Bit Rate)
Playing
30 mA
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IDD, IDL and IPD Test Conditions Figure 10. IDD Test Condition, Active Mode
VDD VDD
RST
VDD PVDD UVDD AVDD
IDD
(NC) Clock Signal
X2 X1 P0 VSS PVSS UVSS AVSS TST
VDD
VSS
All other pins are unconnected
Figure 11. IDL Test Condition, Idle Mode
VDD
RST
VSS
VDD PVDD UVDD AVDD
IDL
(NC) Clock Signal
X2 X1 P0 VSS PVSS UVSS AVSS TST
VDD
VSS
All other pins are unconnected
Figure 12. IPD Test Condition, Power-Down Mode
VDD
RST
VSS
VDD PVDD UVDD AVDD P0 MCMD MDAT TST
IPD
VDD
(NC)
X2 X1 VSS PVSS UVSS AVSS
VSS
All other pins are unconnected
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A to D Converter Table 18. A to D Converter DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol AVDD AIDD Parameter Analog Supply Voltage Analog Operating Supply Current Min 2.7 Typ Max 3.3 Units V A AVDD= 3.3V AIN1:0= 0 to AVDD ADEN= 1 AVDD= 3.3V ADEN= 0 or PD= 1 Test Conditions
600
AIPD AVIN AVREF RREF CIA
Analog Standby Current Analog Input Voltage Reference Voltage AREFN AREFP AREF Input Resistance Analog Input capacitance AVSS AVSS 2.4 10
2 AVDD
A V
V AVDD 30 10 K pF TA= 25C TA= 25C
Oscillator & Crystal Schematic Figure 13. Crystal Connection
X1 C1 Q C2
VSS
X2
Note:
For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 19. Oscillator & Crystal Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol CX1 CX2 CL DL F RS CS Parameter Internal Capacitance (X1 - VSS) Internal Capacitance (X2 - VSS) Equivalent Load Capacitance (X1 - X2) Drive Level Crystal Frequency Crystal Series Resistance Crystal Shunt Capacitance Min Typ 10 10 5 50 20 40 6 Max Unit pF pF pF W MHz pF
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Phase Lock Loop Schematic Figure 14. PLL Filter Connection
FILT R C1
VSS VSS
C2
Parameters
Table 20. PLL Filter Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol R C1 C2 Filter Resistor Filter Capacitance 1 Filter Capacitance 2 Parameter Min Typ 100 10 2.2 Max Unit nF nF
In System Programming Schematic Figure 15. ISP Pull-Down Connection
ISP RISP
VSS
Parameters
Table 21. ISP Pull-Down Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol RISP Parameter ISP Pull-Down Resistor Min Typ 2.2 Max Unit K
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AC Characteristics
External Program Bus Cycles Definition of Symbols Table 22. External Program Bus Cycles Timing Symbol Definitions
Signals A I L P Address Instruction In ALE PSEN H L V X Z Conditions High Low Valid No Longer Valid Floating
Timings
Test conditions: capacitive load on all pins= 50 pF. Table 23. External Program Bus Cycle - Read AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLIV TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to Valid Instruction PSEN Pulse Width PSEN Low to Valid Instruction Instruction Hold After PSEN High Instruction Float After PSEN High Address Valid to Valid Instruction PSEN Low to Address Float 0 TCLCL -10 5*TCLCL -35 10 Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 4*TCLCL-35 3*TCLCL-25 3*TCLCL -35 0 0.5*TCLCL -10 2.5*TCLCL -35 10 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 2*TCLCL-35 1.5*TCLCL-25 1.5*TCLCL -35 Max Unit ns ns ns ns ns ns ns ns ns ns ns
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AT8xC51SND1C
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Waveforms Figure 16. External Program Bus Cycle - Read Waveforms
ALE TLHLL TLLPL PSEN TPLIV TPLAZ TAVLL TLLAX P0 D7:0 A7:0 TPXAV TPXIZ TPXIX D7:0 Instruction In P2 A15:8 A7:0 D7:0 Instruction In A15:8
TPLPH
External Data 8-bit Bus Cycles Definition of Symbols Table 24. External Data 8-bit Bus Cycles Timing Symbol Definitions
Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating
Timings
Test conditions: capacitive load on all pins= 50 pF. Table 25. External Data 8-bit Bus Cycle - Read AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLRL Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to RD Low Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 Max Unit ns ns ns ns ns
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Variable Clock Standard Mode Symbol TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Parameter RD Pulse Width RD high to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to Address Float Data Hold After RD High Instruction Float After RD High 0 2*TCLCL-25 4*TCLCL-30 5*TCLCL-30 0 Min 6*TCLCL-25 TCLCL-20 TCLCL+20 9*TCLCL-65 Max
Variable Clock X2 Mode Min 3*TCLCL-25 0.5*TCLCL-20 0.5*TCLCL +20 4.5*TCLCL-65 2*TCLCL-30 2.5*TCLCL-30 0 0 TCLCL-25 Max Unit ns ns ns ns ns ns ns ns
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Table 26. External Data 8-bit Bus Cycle - Write AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 4*TCLCL-30 7*TCLCL-20 TCLCL-15 TCLCL+20 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 2*TCLCL-30 3.5*TCLCL-20 0.5*TCLCL-15 0.5*TCLCL +20 Max Unit ns ns ns ns ns ns ns ns ns ns
Waveforms
Figure 17. External Data 8-bit Bus Cycle - Read Waveforms
ALE TLHLL
TLLRL
TRLRH
TRHLH
RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D7:0 Data In TRHDZ TRHDX
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Figure 18. External Data 8-bit Bus Cycle - Write Waveforms
ALE TLHLL
TLLWL
TWLWH
TWHLH
WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 TWHQX
External IDE 16-bit Bus Cycles Definition of Symbols Table 27. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating
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Timings Test conditions: capacitive load on all pins= 50 pF. Table 28. External IDE 16-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to RD Low RD Pulse Width RD high to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to Address Float Data Hold After RD High Instruction Float After RD High 0 2*TCLCL-25 4*TCLCL-30 5*TCLCL-30 0 0 TCLCL-25 Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 TCLCL+20 9*TCLCL-65 2*TCLCL-30 2.5*TCLCL-30 0 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 0.5*TCLCL +20 4.5*TCLCL-65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 29. External IDE 16-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 4*TCLCL-30 7*TCLCL-20 TCLCL-15 TCLCL+20 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 2*TCLCL-30 3.5*TCLCL-20 0.5*TCLCL-15 0.5*TCLCL +20 Max Unit ns ns ns ns ns ns ns ns ns ns
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Waveforms
Figure 19. External IDE 16-bit Bus Cycle - Data Read Waveforms
ALE TLHLL
TLLRL
TRLRH
TRHLH
RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D15:8(1) Data In D7:0 Data In TRHDZ TRHDX
Note:
1. D15:8 is written in DAT16H SFR.
Figure 20. External IDE 16-bit Bus Cycle - Data Write Waveforms
ALE TLHLL
TLLWL
TWLWH
TWHLH
WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 D15:8(1) Data Out TWHQX
Note:
1. D15:8 is the content of DAT16H SFR.
SPI Interface
Definition of Symbols Table 30. SPI Interface Timing Symbol Definitions
Signals C I O Clock Data In Data Out H L V X Z Conditions High Low Valid No Longer Valid Floating
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Timings Test conditions: capacitive load on all pins= 50 pF. Table 31. SPI Interface Master AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol Parameter Slave Mode TCHCH TCHCX TCLCX TSLCH, TSLCL TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TCLSH, TCHSH TSLOV TSHOX TSHSL TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time SS Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge SS High after Clock Edge SS Low to Output Data Valid Output Data Hold after SS High SS High to SS Low Input Rise Time Input Fall Time Output Rise time Output Fall Time Master Mode TCHCH TCHCX TCLCX TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge Input Data Rise Time Input Data Fall Time Output Data Rise time Output Data Fall Time 0 2 2 50 50 2 0.8 0.8 20 20 40 TPER TPER TPER ns ns ns ns s s ns ns
(1)
Min
Max
Unit
2 0.8 0.8 100 40 40 40 0 0 50 50
TPER TPER TPER ns ns ns ns ns ns ns ns
2 2 100 100
s s ns ns
Note:
1. Value of this parameter depends on software.
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Waveforms
Figure 21. SPI Slave Waveforms (SSCPHA= 0)
SS (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output) SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOV TCHOV BIT 6 TCHCH TCLCH
TCLSH TCHSH
TSHSL
TCHCX
TCLCX TCHCL
TCLOX TCHOX SLAVE LSB OUT
(1)
TSHOX
Note:
1. Not Defined but generally the MSB of the character which has just been received.
Figure 22. SPI Slave Waveforms (SSCPHA= 1)
SS (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output)
(1)
TCHCH
TCLCH
TCLSH TCHSH
TSHSL
TCHCX
TCLCX TCHCL
TCHOV TCLOV BIT 6
TCHOX TCLOX SLAVE LSB OUT
TSHOX
SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX
MOSI (input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the LSB of the character which has just been received.
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Figure 23. SPI Master Waveforms (SSCPHA= 0)
SS (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TCLCH
TCHCX
TCLCX TCHCL
TIVCH TCHIX TIVCL TCLIX MSB IN BIT 6 TCLOV TCHOV LSB IN TCLOX TCHOX LSB OUT Port Data
MOSI (input)
MISO (output)
Port Data
MSB OUT
BIT 6
Note:
1. SS handled by software using general purpose port pin.
Figure 24. SPI Master Waveforms (SSCPHA= 1)
SS(1) (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TCLCH
TCHCX
TCLCX TCHCL
TIVCH TCHIX TIVCL TCLIX
MOSI (input)
MSB IN TCLOV
BIT 6 TCLOX TCHOX BIT 6
LSB IN
MISO (output)
TCHOV Port Data MSB OUT
LSB OUT
Port Data
Note:
1. SS handled by software using general purpose port pin.
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Two-wire Interface Timings Table 32. TWI Interface AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C
INPUT Min Max 14*TCLCL(4) 16*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s 250 ns 250 ns 250 ns 0 ns 14*TCLCL(4) 14*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s OUTPUT Min Max 4.0 s(1) 4.7 s(1) 4.0 s(1) -(2) 0.3 s(3) 20*TCLCL(4)- TRD 1 s(1) 8*TCLCL(4) 8*TCLCL(4) - TFC 4.7 s(1) 4.0 s(1) 4.7 s(1) -(2) 0.3 s(3)
Symbol THD; STA TLOW THIGH TRC TFC TSU; DAT1 TSU; DAT2 TSU; DAT3 THD; DAT TSU; STA TSU; STO TBUF TRD TFD
Parameter Start condition hold time SCL low time SCL high time SCL rise time SCL fall time Data set-up time SDA set-up time (before repeated START condition) SDA set-up time (before STOP condition) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time SDA fall time
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3*TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC= one oscillator clock period.
Waveforms
Figure 25. Two Wire Waveforms
Repeated START condition START condition STOP condition Tsu ;STA 0.7 VDD 0.3 VDD Tfd Trc SCL (INPUT/OUTPUT) Thd;STA Tlow Thigh Tsu;DAT Thd;DAT Tsu;DAT2 Tfc Tsu;STO Tsu;DAT3 0.7 VDD 0.3 VDD Tbuf
START or Repeated START condition Trd SDA (INPUT/OUTPUT)
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MMC Interface Definition of symbols Table 33. MMC Interface Timing Symbol Definitions
Signals C D O Clock Data In Data Out H L V X Conditions High Low Valid No Longer Valid
Timings
Table 34. MMC Interface AC timings VDD = 2.7 to 3.3 V, TA = -40 to +85C, CL 100pF (10 cards)
Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TDVCH TCHDX TCHOX TOVCH Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Input Data Valid to Clock High Input Data Hold after Clock High Output Data Hold after Clock High Output Data Valid to Clock High 3 3 5 5 Parameter Min 50 10 10 10 10 Max Unit ns ns ns ns ns ns ns ns ns
Waveforms
Figure 26. MMC Input-Output Waveforms
TCHCH TCHCX MCLK TCHCL TCHIX MCMD Input MDAT Input TCHOX MCMD Output MDAT Output TOVCH TCLCH TIVCH TCLCX
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Audio Interface Definition of symbols Table 35. Audio Interface Timing Symbol Definitions
Signals C O S Clock Data Out Data Select H L V X Conditions High Low Valid No Longer Valid
Timings
Table 36. Audio Interface AC timings VDD = 2.7 to 3.3 V, TA = -40 to +85C, CL 30pF
Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TCLSV TCLOV Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Clock Low to Select Valid Clock Low to Data Valid 30 30 10 10 10 10 Min Max 325.5(1) Unit ns ns ns ns ns ns ns
Note:
1. 32-bit format with Fs= 48 KHz.
Waveforms
Figure 27. Audio Interface Waveforms
TCHCH TCHCX DCLK TCHCL TCLSV DSEL TCLOV DDAT Right Left TCLCH TCLCX
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AT8xC51SND1C
Analog to Digital Converter Definition of symbols Table 37. Analog to Digital Converter Timing Symbol Definitions
Signals C E S Clock Enable (ADEN bit) Start Conversion (ADSST bit) H L Conditions High Low
Characteristics
Table 38. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol TCLCL TEHSH TSHSL DLe Parameter Clock Period Start-up Time Conversion Time Differential nonlinearity error(1)(2) Integral nonlinearity errorss (1)(3) Offset error(1)(4) Gain error(1)(5) Min 4 4 11*TCLCL 1 Max Unit s s s LSB
ILe OSe Ge
2 4 4
LSB LSB LSB
Notes:
1. AVDD= AVREFP= 3.0 V, AVSS= AV REFN= 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 29). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 29). 4. The offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see Figure 29). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see Figure 29).
Waveforms
Figure 28. Analog to Digital Converter Internal Waveforms
CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL
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4109FS-8051-01/04
Figure 29. Analog to Digital Converter Characteristics
Code Out
Offset Gain Error Error OSe Ge
1023 1022 1021 1020 1019 1018 Ideal Transfer curve
7 6 5 4 3 2 1 0 0 1 LSB (ideal) 1 Offset Error OSe 2 3 4 5 6 7 Center of a step
Example of an actual transfer curve
Integral non-linearity (ILe) Differential non-linearity (DLe)
1018 1019 1020 1021 1022 1023 1024
AVIN (LSB ideal)
Flash Memory Definition of symbols Table 39. Flash Memory Timing Symbol Definitions
Signals S R B ISP RST FBUSY flag L V X Conditions Low Valid No Longer Valid
Timings
Table 40. Flash Memory AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol TSVRL TRLSX TBHBL NFCY TFDR Parameter Input ISP Valid to RST Edge Input ISP Hold after RST Edge FLASH Internal Busy (Programming) Time Number of Flash Write Cycles Flash Data Retention Time 100K 10 Min 50 50 10 Typ Max Unit ns ns ms Cycle Years
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Waveforms Figure 30. FLASH Memory - ISP Waveforms
RST TSVRL ISP
(1)
TRLSX
Note:
1. ISP must be driven through a pull-down resistor (see Section "In System Programming", page 33).
Figure 31. FLASH Memory - Internal Busy Waveforms
FBUSY bit
TBHBL
External Clock Drive and Logic Level References Definition of symbols Table 41. External Clock Timing Symbol Definitions
Signals C Clock H L X Conditions High Low No Longer Valid
Timings
Table 42. External Clock AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCR Clock Period High Time Low Time Rise Time Fall Time Cyclic Ratio in X2 mode Parameter Min 50 10 10 3 3 40 60 Max Unit ns ns ns ns ns %
Waveforms
Figure 32. External Clock Waveform
TCLCH VDD - 0.5 0.45 V VIH1 TCLCX TCHCL TCLCL TCHCX
VIL
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4109FS-8051-01/04
Figure 33. AC Testing Input/Output Waveforms
INPUTS VDD - 0.5 0.45 V 0.7 VDD 0.3 VDD OUTPUTS VIH min VIL max
Note:
1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 34. Float Waveforms
VLOAD VLOAD + 0.1 V VLOAD - 0.1 V Timing Reference Points VOH - 0.1 V VOL + 0.1 V
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/V OL level occurs with IOL/IOH= 20 mA.
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Ordering Information
Memory Size
64K Flash 64K Flash 64K ROM 64K ROM ROMless ROMless
Part Number
AT89C51SND1C-ROTIL AT89C51SND1C-7HTIL AT83SND1Cxxx(1) -ROTIL AT83SND1Cxxx(1)-7HTIL AT80C51SND1C-ROTIL AT80C51SND1C-7HTIL
Supply Voltage
3V 3V 3V 3V 3V 3V
Temperature Range
Industrial Industrial Industrial Industrial Industrial Industrial
Max Frequency
40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz
Package(2)
TQFP80 BGA81 TQFP80 BGA81 TQFP80 BGA81
Packing
Tray Tray Tray Tray Tray Tray
Product Marking
89C51SND1C-IL 89C51SND1C-IL 89C51SND1C-IL 89C51SND1C-IL 89C51SND1C-IL 89C51SND1C-IL
Notes:
1. Refers to ROM code. 2. PLCC84 package only available for development board.
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4109FS-8051-01/04
Package Information
TQFP80
52
AT8xC51SND1C
4109FS-8051-01/04
AT8xC51SND1C
BGA81
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4109FS-8051-01/04
PLCC84
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AT8xC51SND1C
4109FS-8051-01/04
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4109FS-8051-01/04 /0M

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